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MC14490 Hex Contact Bounce Eliminator
The MC14490 is constructed with complementary MOS enhancement mode devices, and is used for the elimination of extraneous level changes that result when interfacing with mechanical contacts. The digital contact bounce eliminator circuit takes an input signal from a bouncing contact and generates a clean digital signal four clock periods after the input has stabilized. The bounce eliminator circuit will remove bounce on both the "make" and the "break" of a contact closure. The clock for operation of the MC14490 is derived from an internal R-C oscillator which requires only an external capacitor to adjust for the desired operating frequency (bounce delay). The clock may also be driven from an external clock source or the oscillator of another MC14490 (see Figure 5). NOTE: Immediately after power-up, the outputs of the MC14490 are in indeterminate states.
http://onsemi.com MARKING DIAGRAMS
16 PDIP-16 P SUFFIX CASE 648 1 16 SOIC-16 DW SUFFIX CASE 751G 1 16 SOEIAJ-16 F SUFFIX CASE 966 MC14490 AWLYWW 14490 MC14490P AWLYYWW
* * * * * * * * * * * *
Diode Protection on All Inputs Six Debouncers Per Package Internal Pullups on All Data Inputs Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line Internal Oscillator (R-C), or External Clock Source TTL Compatible Data Inputs/Outputs Single Line Input, Debounces Both "Make" and "Break" Contacts Does Not Require "Form C" (Single Pole Double Throw) Input Signal Cascadable for Longer Time Delays Schmitt Trigger on Clock Input (Pin 7) Supply Voltage Range = 3.0 V to 18 V Chip Complexity: 546 FETs or 136.5 Equivalent Gates
AWLYYWW
1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
ORDERING INFORMATION
Device MC14490DW Package SOIC-16 SOIC-16 SOEIAJ-16 SOEIAJ-16 PDIP-16 Shipping 47/Rail 1000/Tape & Reel See Note 1. See Note 1. 25/Rail
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 Unit V V mA mW C C C
MC14490DWR2 MC14490F MC14490FEL MC14490P
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C
v
v
(c) Semiconductor Components Industries, LLC, 2000
1
May, 2000 - Rev. 4
Publication Order Number: MC14490/D
MC14490
PIN ASSIGNMENT
Ain Bout Cin Dout Ein Fout OSCin VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Aout Bin Cout Din Eout Fin OSCout
BLOCK DIAGRAM
+VDD DATA 4-BIT STATIC SHIFT REGISTER SHIFT OSCin 7 OSCout 9 Bin 14 Cin 3 Din 12 Ein 5 Fin 10 OSCILLATOR AND TWO-PHASE CLOCK GENERATOR 1 2 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 2 6 Fout 2 11 Eout 2 4 Dout 2 13 Cout LOAD 1 2 1 2 2 Bout 1 2 VDD = PIN 16 VSS = PIN 8 1/2-BIT DELAY 15 Aout
Ain 1
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II IIII I IIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I III II IIII I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II II IIII I I II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Quiescent Current (Vin = VSS or VDD, Iout = 0 A)
Input Capacitance
Pullup Resistor Source Current Debounce Inputs (Vin = VSS)
Input Current Oscillator -- Pin 7 (Vin = VSS or VDD)
Input Current Debounce Inputs (Vin = VDD)
Output Drive Current Oscillator Output (VOH = 2.5 V) (VOH = 4.6 V) (VOH = 9.5 V) (VOH = 13.5 V)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc) "1 Level" (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)
Debounce Outputs (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V)
Oscillator Output (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V)
Debounce Outputs (VOH = 2.5 V) (VOH = 4.6 V) (VOH = 9.5 V) (VOH = 13.5 V)
Characteristic
"0" Level
"1" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
ISS
Cin
IOL
VIL
IIH
IIL
Iin
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
15
--
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- 0.9 - 0.19 - 0.6 1.8 - 0.6 - 0.12 - 0.23 - 1.4 4.95 9.95 14.95 0.36 0.9 4.2 Min 175 340 505 2.6 4.0 12 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- --
MC14490
- 55_C
3 620 375 740 1100 0.05 0.05 0.05 Max 150 280 840 2.0 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 0.75 - 0.16 - 0.5 - 1.5 4.95 9.95 14.95 - 0.5 - 0.1 - 0.2 - 1.2 0.3 0.75 3.5 Min 140 280 415 2.2 3.3 10 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- Typ - 2.2 - 0.46 - 1.2 - 4.5 255 25_C - 1.5 - 0.3 - 0.8 - 3.0 2.75 5.50 8.25 2.25 4.50 6.75 40 90 225 5.0 0.2 4.0 9.0 35 0.9 2.3 10 5.0 10 15 0 0 0 190 380 570
(4.)
400
0.05 0.05 0.05
Max
100 225 650 255 500 750 7.5 2.0 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- 0.6 - 0.12 - 0.4 - 1.2
- 0.4 - 0.08 - 0.16 - 1.0
4.95 9.95 14.95
0.24 0.6 2.8
Min
70 145 215
1.8 2.7 8.1
3.5 7.0 11
-- -- -- -- -- -- -- -- -- -- -- --
125_C
250
0.05 0.05 0.05
Max
90 180 550 1.5 3.0 4.0 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
225 440 660
mAdc
mAdc
Adc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
MC14490
SWITCHING CHARACTERISTICS (5.) (CL = 50 pF, TA = 25_C)
III I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII III I I I I I IIIIII IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIII
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ (6.) 180 90 65 100 50 40 60 30 20 Max 360 180 130 200 100 80 120 60 40 570 240 190 740 320 240 1.4 3.0 4.5 -- -- -- Unit ns Output Rise Time All Outputs Output Fall Time Oscillator Output ns tTHL tTHL Debounce Outputs Propagation Delay Time Oscillator Input to Debounce Outputs tPHL 285 120 95 370 160 120 2.8 6 9 50 40 30 ns tPLH Clock Frequency (50% Duly Cycle) (External Clock) Setup Time (See Figure 1) fcl MHz tsu 100 80 60 ns Maximum External Clock Input Rise and Fall Time Oscillator Input Oscillator Frequency OSCout Cext 100 pF* tr, tf ns No Limit fosc, typ 1.5 C ext (in mF) 4.5 C ext (in mF) 6.5 C ext (in mF) Hz Note: These equations are intended to be a design guide. Laboratory experimentation may be required. Formulas are typically 15% of actual frequencies. 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
*POWER-DOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the turn-off time of the power supply must not be faster than t = (VDD - VSS) Cext / (10 mA). For example, If VDD - VSS = 15 V and Cext = 1 F, the power supply must turn off no faster than t = (15 V) (1 F) / 10 mA = 1.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
OSCin tPLH Aout 50% 50% 90% 10% tr tPHL Aout 90% 10% 50% tf OSCin Ain 50% tsu 50% VDD 0V VDD 0V VDD 0V D1 VDD 7 OSCin 9 OSCout Cext D2 VDD
MC14490
Figure 1. Switching Waveforms
Figure 2. Discharge Protection During Power Down http://onsemi.com
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MC14490
THEORY OF OPERATION The MC14490 Hex Contact Bounce Eliminator is basically a digital integrator. The circuit can integrate both up and down. This enables the circuit to eliminate bounce on both the leading and trailing edges of the signal, shown in the timing diagram of Figure 3. Each of the six Bounce Eliminators is composed of a 4-1/2-bit register (the integrator) and logic to compare the input with the contents of the shift register, as shown in Figure 4. The shift register requires a series of timing pulses in order to shift the input signal into each shift register location. These timing pulses (the clock signal) are represented in the upper waveform of Figure 3. Each of the six Bounce Eliminator circuits has an internal resistor as shown in Figure 4. A pullup resistor was incorporated rather than a pulldown resistor in order to implement switched ground input signals, such as those coming from relay contacts and push buttons. By switching ground, rather than a power supply lead, system faults (such as shorts to ground on the signal input leads) will not cause excessive currents in the wiring and contacts. Signal lead shorts to ground are much more probable than shorts to a power supply lead. When the relay contact is closed, (see Figure 4) the low level is inverted, and the shift register is loaded with a high on each positive edge of the clock signal. To understand the operation, we assume all bits of the shift register are loaded with lows and the output is at a high level. At clock edge 1 (Figure 3) the input has gone low and a high has been loaded into the first bit or storage location of the shift register. Just after the positive edge of clock 1, the input signal has bounced back to a high. This causes the shift register to be reset to lows in all four bits -- thus starting the timing sequence over again. During clock edges 3 to 6 the input signal has stayed low. Thus, a high has been shifted into all four shift register bits and, as shown, the output goes low during the positive edge of clock pulse 6. It should be noted that there is a 3-1/2 to 4-1/2 clock period delay between the clean input signal and output signal. In this example there is a delay of 3.8 clock periods from the beginning of the clean input signal. After some time period of N clock periods, the contact is opened and at N +1 a low is loaded into the first bit. Just after N+1, when the input bounces low, all bits are set to a high. At N +2 nothing happens because the input and output are low and all bits of the shift register are high. At time N +3 and thereafter the input signal is a high, clean signal. At the positive edge of N +6 the output goes high as a result of four lows being shifted into the shift register. Assuming the input signal is long enough to be clocked through the Bounce Eliminator, the output signal will be no longer or shorter than the clean input signal plus or minus one clock period. The amount of time distortion between the input and output signals is a function of the difference in bounce characteristics on the edges of the input signal and the clock frequency. Since most relay contacts have more bounce when making as compared to breaking, the overall delay, counting bounce period, will be greater on the leading edge of the input signal than on the trailing edge. Thus, the output signal will be shorter than the input signal -- if the leading edge bounce is included in the overall timing calculation. The only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state. Referring to Figure 3, a false state is seen to occur three times at the beginning of the input signal. The input signal goes low three times before it finally settles down to a valid low state. The first three low pulses are referred to as false states. If the user has an available clock signal of the proper frequency, it may be used by connecting it to the oscillator input (pin 7). However, if an external clock is not available the user can place a small capacitor across the oscillator input and output pins in order to start up an internal clock source (as shown in Figure 4). The clock signal at the oscillator output pin may then be used to clock other MC14490 Bounce Eliminator packages. With the use of the MC14490, a large number of signals can be cleaned up, with the requirement of only one small capacitor external to the Hex Bounce Eliminator packages.
1 OSCin OR OSCout
2
3
4
5
6
N+1
N+3
N+5
N+7
INPUT
OUTPUT
CONTACT OPEN CONTACT BOUNCING
CONTACT CLOSED (VALID TRUE SIGNAL)
CONTACT OPEN CONTACT BOUNCING
Figure 3. Timing Diagram http://onsemi.com
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MC14490
+VDD Ain 1 "FORM A" CONTACT OSCin 7 Cext OSCout 9 PULLUP RESISTOR (INTERNAL)
DATA 4-BIT STATIC SHIFT REGISTER SHIFT LOAD
1/2 BIT DELAY 1 2
15 Aout
OSCILLATOR AND TWO-PHASE CLOCK GENERATOR
1 2
1 2
Figure 4. Typical "Form A" Contact Debounce Circuit (Only One Debouncer Shown)
OPERATING CHARACTERISTICS The single most important characteristic of the MC14490 is that it works with a single signal lead as an input, making it directly compatible with mechanical contacts (Form A and B). The circuit has a built-in pullup resistor on each input. The worst case value of the pullup resistor (determined from the Electrical Characteristics table) is used to calculate the contact wetting current. If more contact current is required, an external resistor may be connected between VDD and the input. Because of the built-in pullup resistors, the inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V. At this voltage, the input should be driven with paralleled standard gates or by the MC14049 or MC14050 buffers. The clock input circuit (pin 7) has Schmitt trigger shaping such that proper clocking will occur even with very slow clock edges, eliminating any need for clock preshaping. In addition, other MC14490 oscillator inputs can be driven from a single oscillator output buffered by an MC14050 (see Figure 5). Up to six MC14490s may be driven by a single buffer. The MC14490 is TTL compatible on both the inputs and the outputs. When VDD is at 4.5 V, the buffered outputs can sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a result of the internal input pullup resistors.
OSCin 7 Cext 1/6 MC14050
NO CONNECTION 9 OSCout
OSCin
7
9
OSCout
FROM CONTACTS
MC14490
TO SYSTEM LOGIC
FROM CONTACTS
MC14490
TO SYSTEM LOGIC
OSCin 7
NO CONNECTION 9 OSCout
FROM CONTACTS
MC14490
TO SYSTEM LOGIC
Figure 5. Typical Single Oscillator Debounce System
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MC14490
TYPICAL APPLICATIONS
ASYMMETRICAL TIMING MULTIPLE TIMING SIGNALS
In applications where different leading and trailing edge delays are required (such as a fast attack/slow release timer.) Clocks of different frequencies can be gated into the MC14490 as shown in Figure 6. In order to produce a slow attack/fast release circuit leads A and B should be interchanged. The clock out lead can then be used to feed clock signals to the other MC14490 packages where the asymmetrical input/output timing is required.
IN OUT
OSCin
MC14490
OSCout
MC14011B
As shown in Figure 8, the Bounce Eliminator circuits can be connected in series. In this configuration each output is delayed by four clock periods relative to its respective input. This configuration may be used to generate multiple timing signals such as a delay line, for programming other timing operations. One application of the above is shown in Figure 9, where it is required to have a single pulse output for a single operation (make) of the push button or relay contact. This only requires the series connection of two Bounce Eliminator circuits, one inverter, and one NOR gate in order to generate the signal AB as shown in Figures 9 and 10. The signal AB is four clock periods in length. If the inverter is switched to the A output, the pulse AB will be generated upon release or break of the contact. With the use of a few additional parts many different pulses and waveshapes may be generated.
1 B.E. 1 15 Aout
A EXTERNAL CLOCK fC /N
B fC/N
Ain
14 Bin
B.E. 2
2
Bout
Figure 6. Fast Attack/Slow Release Circuit
3 13 B.E. 3 Cin 12 Din 5 Ein IN OUT 10 MC14490 OSCin OSCout MC14011B CLOCK LATCH = 1 UNLATCH = 0 OSCin 7 CLOCK 9 OSCout Fin B.E. 6 6 Fout 11 4
LATCHED OUTPUT
Cout
The contents of the Bounce Eliminator can be latched by using several extra gates as shown in Figure 7. If the latch lead is high the clock will be stopped when the output goes low. This will hold the output low even though the input has returned to the high state. Any time the clock is stopped the outputs will be representative of the input signal four clock periods earlier.
B.E. 4
Dout
B.E. 5
Eout
Figure 8. Multiple Timing Circuit Connections
Figure 7. Latched Output Circuit
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MC14490
IN A IN BE 2 A ACTIVE LOW B ACTIVE LOW OUT B BE 1 OUT A B AB
Figure 9. Single Pulse Output Circuit
OSCin OR OSCout
INPUT
A
B
C
D
E
F
AB
AB
Figure 10. Multiple Output Signal Timing Diagram
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MC14490
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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MC14490
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14490
PACKAGE DIMENSIONS
SOIC-16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1
8
16X
B TA
S
B B
S
h X 45 _
M
8X
0.25
E
0.25
M
A1
14X
e
SEATING PLANE
DIM A A1 B C D E e H h L
A
L
T
C
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MC14490
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MC14490/D

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